1. Field of the Invention
The present invention relates to a multilayer ceramic capacitor for three-dimensional mounting suitable for mounting in a personal computer or other electronic apparatus with a high operating frequency as a low equivalent serial inductance (ESL) and low equivalent serial resistance (ESR) capacitor and suitable for mounting on a three-dimensional multilayer printed circuit board.
2. Description of the Related Art
In the past, as multiterminal multilayer ceramic capacitors, for example the capacitor disclosed in U.S. Pat. No. 5,880,925 is known. This capacitor has a capacitor body which has two types of, that is, first and second, internal electrodes and dielectric layers stacked to sandwich them. Each of these internal electrodes is formed with a rectangular main portion pattern extending in the longitudinal direction on a face of a rectangular ceramic layer and a plurality of lead patterns extending from the sides of the main portion to the sides of the ceramic layer. The lead patterns of the first internal electrodes and the lead patterns of the second internal electrodes are formed at different positions from each other when seen from a plan view. A plurality of external electrodes are formed at the side faces of the long and short sides of the capacitor body of this multiterminal multilayer ceramic capacitor.
This multiterminal multilayer ceramic capacitor is placed on the surface of a circuit board so that the external electrodes are positioned in a standing direction from the surface of the circuit board. The stacking direction of the internal electrodes and the ceramic layers are substantially vertical to the circuit board. The external electrodes are joined and fixed by soldering to the lands of the circuit pattern of the circuit board so as to mount the capacitor on the surface of the circuit board.
In this type of multilayer ceramic capacitor, however, since the stacking direction of the internal electrodes and the ceramic layers is made to register with the height direction of the capacitor for the surface mounting, if the number of ceramic layers stacked is increased from the electrical characteristics required, the height of the electronic devices cannot be kept low.
Note that as multilayer electronic devices for surface mounting by bringing the stacking direction of the ceramic layers into register with the height direction of the multilayer electronic device, in addition to the one of U.S. Pat. No. 5,880,925, there are many known such as those disclosed in Japanese Examined Patent Publication (Kokoku) No. 64-10927, Japanese Unexamined Patent Publication (Kokai) No. 7-161568, Japanese Unexamined Patent Publication (Kokai) No. 7-169649, Japanese Unexamined Patent Publication (Kokai) No. 7-169651, Japanese Unexamined Patent Publication (Kokai) No. 7-272975, Japanese Unexamined Patent Publication (Kokai) No. 8-124800, Japanese Unexamined Patent Publication (Kokai) No. 9-148174, Japanese Unexamined Utility Model Publication (Kokai) No. 6-7228, Japanese Examined Patent Publication (Kokoku) No. 62-35257, and Japanese Examined Patent Publication (Kokoku) No. 63-38856. In a multilayer electronic device for surface mounting by bringing the stacking direction of the ceramic layers into register with the height direction of the multilayer electronic device, there is the problem that, if the number of ceramic layers stacked is increased from the electrical characteristics required, it is not possible to keep low the height of the electronic device.
In personal computers and other electronic apparatuses, however, the operating frequency has increased from 500 MHz to 1 GHz. The power supply circuit is required to be a low ESL and low ESR multilayer ceramic capacitor. Further, in view of the increasingly smaller sizes of electronic apparatuses, a multiterminal multilayer ceramic capacitor which keeps the height dimension low, enables reliable surface mounting on a three-dimensional printed circuit board etc., and gives predetermined characteristics has been demanded.
If three-dimensionally mounting a conventional multiterminal multilayer ceramic capacitor on a three-dimensional multilayer printed circuit board etc., however, the circuit pattern formed on the circuit board becomes longer, the detouring of the lands becomes longer, and there is a detrimental effect on the inductance component. In particular, a circuit pattern comprised of lands at upper positions and lands at lower positions becomes longer, the detouring of the lands becomes longer and has a detrimental effect on the inductance component, and generation of noise becomes unavoidable.
Further, if surface mounting the conventional capacitor near the terminals of a semiconductor etc. to lower the ESL, there is the problem that the effect of the inductance component due to the detouring of the lands cannot be ignored. Further, in a conventional capacitor, as explained above, the height dimension of the capacitor itself cannot be kept low no matter what the number of layers stacked. From this, the conventional capacitor is not suited for three-dimensional mounting.
Note that as shown in Japanese Unexamined Patent Publication (Kokai) No. 57-60827 (corresponding to U.S. patent application Ser. No. 167,191 filed on Jul. 9, 1980) and Japanese Patent No. 2657953 (corresponding to U.S. patent application Ser. No. 212,361 filed on Jun. 27, 1988), a capacitor in which the stacking direction of the ceramic layers is brought into register with the planar direction of the circuit board on which the multilayer ceramic capacitor is to be surface mounted has been proposed. The capacitors disclosed in these publications, however, has the problems that the capacitors cannot be three-dimensionally mounted and the ESR and/or ESL of the external circuits connected to the capacitors easily become large.